FAST mode for the ZX82, anyone?

[1bvl109]

The ULA generates the control signals for the "lower" RAM accesses (/RAS, /CAS and the control for the address multiplexers) which in turn control the DRAM chips. So what happens if the CPU writes data just as the ULA sets up an address to read screen data? Will the write data go to an address it is not supposed to go to?

Ok, that would be fatal.

It may well be that the ULA is designed to give priority to the CPU, but as this problem never normally occurs, it's not possible to say for certain.

Me thinks it could have been constructed this way. You just have to look for

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A15=0 AND A14=1 AND /MREQ=0

on the Z80 bus, which only uses a few gates and than give precedence to producing /RAS, /CAS.
However concerning "just a few gates more" I'm not sure how much more would have fitted in. If I look at the very partial decoding of the IO-ports I wonder if that was done, because they were already at the limit concerning the number of gates. Sevven.FFF here viewtopic.php?f=6&t=1709&p=24308#p24308 says, that Chris Smith says, this was actually the case.
Couldn't you at least contend only the lowest 8K if RAM, i.e.

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A15=0 AND A14=1 AND A13=0

as the whole screen is in there?

During the time that the ULA is "drawing the video picture", the regular accesses by their nature, perform refresh. But although it was intended for the Z80 to refresh this RAM during the rest of the time, due to a design error inside the ULA, it ignores the Z80's attempts at refresh

Thanks. I never knew.

... the ULA stops the CPU by holding it's clock line. As the clock input to the Z80 is held, the CPU stops....

Um ... I knew this ... sorry. It's been a long time. Thanks for reminding me.

My, "if only" is, if Sinclair had used a single 74LS series latch chip to read the keyboard lines, this would have feed some much needed ULA pins from being dedicated to being keyboard inputs. What could have been done with 4 "spare" ULA pins?

In case of more RAM-banks we would have needed some lines, to switch between them of course. But I don't get it what exactly you want to do with a latch. I always thought something like a decoder/encoder was missing on the keyboard lines, say a 74138.

My second and third are: why no edge-connector signal to disable internal RAM ('cus no one thought it was needed) ...

Probably

and why use up HALF the Z80 CPU I/O address space, by the ULA only using one address line for decoding (and they messed this up).

Immense pressure to reach the deadline I assume.

[ZXDunny]

Somewhat related, iirc you can demonstrate DRAM fading on a speccy. It's here: https://fms.komkon.org/stuff/spectrum.faq

In the section on the R Register. I don't believe any emulators can reproduce this effect.

[1bvl109]

80K of RAM would've been insanely expensive in 1982, certainly not something that would have been on the radar for a dirt cheap home computing device.

I'm not so sure about this. Most of the ZX81 guys i knew bought 16K, the others bought 64K. For purpose of dirt cheap the Spectrum was at a factor of 3, while the 81 was at 16 at least. Hook them at dirt cheap and use the cry for more to cash in later.
For similar reason I disliked the QL for forcing us to buy two microdrives instead of throwing in a dirt cheap tape interface. Oh sure loading would have been a pain in one's posterior, but it would have been THE budget machine at he start of the 16 bit era.
Just think that Sinclair would have squashed Commodore. Like a fly. And Atari. And been steamrollered by the PC anyway. Oh well.

[djnzx48]

There was a recent discussion about DRAM fading here: https://zx-pk.ru/threads/30593-rasprede ... myati.html

There was also talk about trying to get the effect emulated accurately, but I don't know how much progress was made.

[1024MAK]

Couldn't you at least contend only the lowest 8K if RAM, i.e.

Code: Select all

A15=0 AND A14=1 AND A13=0

as the whole screen is in there?

The thing that determines the difference between contended RAM and non-contended RAM, is the different physical RAM chips and the two different busses (that’s why there are resistors in the data lines). The DRAM chips used can only service one device at a time. When the CPU communicates with the “upper” RAM, the resistors allow the Z80 and the ULA to both access the different DRAM banks at the same time.

But I don't get it what exactly you want to do with a latch. I always thought something like a decoder/encoder was missing on the keyboard lines, say a 74138.

Well, it doesn’t have to be a latch, a set of gates with tristate output buffers would do. See the ZX80 schematic for an example.

Yes you could use a 3 to 8 line decoder like a 74LS138. But instead Sinclair used the upper address lines, taking advantage of the Z80 IN instruction actually driving all 16 address lines.

Mark