Spectrum Next core on MiSTer fpga?

[antoniovillena]

I buy from digikey and mouser, mostly digikey. About 20 units of de10 nano every week. This is my current stock

[antoniovillena]

Assuming this is the correct part, they are for me £53.99 with free UK shipping.

https://misterfpga.co.uk/product/mister ... mb-module/

This not the correct part. Next core needs SRAM memory. That module is only SDRAM. There is no official part for 32MB+2MB module. This is the part:

https://github.com/MiSTer-devel/Hardwar ... SDRAM_SRAM

It's a prototype developped by Sorgelig 3 years ago. It costs 38 EUR without shipping. So the total is at least 183 EUR without shipping. That's for a limited MiSTer (not all NeoGeo games available) without case, without IO addon (analog outputs), without hub, but capable to run Next core

[PeterJ]

I buy from digikey and mouser, mostly digikey. About 20 units of de10 nano every week. This is my current stock

Thanks for the correction [mention]antoniovillena[/mention].

Wow, can I play Jenga please!

[ZXDunny]

Damn. Now I'm wondering if once the SRAM issue is resolved I might be able to run a MiSTer inside a Next case for the ultimate in FPGA fun.

[Seven.FFF]

The Next design pushes async SRAM access patterns beyond what sequential SDRAM can keep up with. Typical solutions like SDRAM cache don't work well enough here, because much of the timing pressure comes from video RAM, which can't slow down the machine when cache misses occur. Misses would give video glitches or sparkles. Most of the Next's video RAM is in fast BRAM inside the FPGA, but because of the way layer 2 can be moved around over almost the entire memory map within a few Ts to facilitate multiple back buffers, at least 1792KB of SDRAM would need to be cached, which is unfeasible. DMA is another pressure on the timings, but this has a sequential pattern so a fancy cache algorithm with privileged knowledge of the DMA program might be able to do DMA without too much slowdown. Because of the first issue, I'm not expecting SDRAM to be implemented for the Next core any time soon (although I will be pleased if it is!). Perhaps it can with higher speed SDRAM, but that doesn't help the MISTer.

[akeley]

Well, I was quietly hoping for this core to appear on a basic MiSTer, but I guess you can't have everything

It's supposed to work with this special SDRAM module: https://manuferhi.com/p/dual-memory-for ... b-2mb-sram
Costs ~40E though, which is a bit dear for those like me who already have normal SDRAM. Unless you're building a new one...

Or I guess I could try to sell mine and get this one. Hmmm. Have to mull it over...

[Seven.FFF]

It's supposed to work with this special SDRAM module: https://manuferhi.com/p/dual-memory-for ... b-2mb-sram
Costs ~40E though, which is a bit dear for those like me who already have normal SDRAM. Unless you're building a new one...

Yes, this is the current workaround that makes it possible at all. It is using the extra SRAM inside that module, not the SDRAM. I guess they made it a dual module so it's also useful for other MISTer cores that use SDRAM without having to constantly switch modules.

The real issue here is that base board hardware (outside the FPGA) has some real effect on the kind of machines you can design or implement with it. MISTer is coming from a background where designs are friendly to sequential access from the beginning, whereas Next design is coming from a background where async access is pushed close to a limit without considering how to make it sequential-friendly.