Contention pattern for HALT

[Patrik Rak]

Fair enough.

[ketmar]

by the way, i am Teh Official Idiot. what Patrik says in the following quote is not only right, but the official Zilog manual explicitly says exactly that — and i should have read the manual before trying to reply anything.

Only the first fetch of the HALT itself. Then it executes NOPs internally, with PC already being PC+1.

(So it's not like it keeps executing itself similar to LDIR, which is what people originally believed.)

Zilog manual:
The purpose of executing NOP instructions while in the HALT state is to keep the memory refresh signals active. Each cycle in the HALT state is a normal M1 (fetch) cycle except that the data received from the memory is ignored and an NOP instruction is forced internally to the CPU.

that is, Z80 sets all the signals as usual ("normal M1 (fetch) cycle"), but it skips sampling the data bus (which still contains the read opcode), and the whole instruction decoding. this is also why PC is not advanced further (no decode). it still puts refresh address on A0-A6 and increments R, though.