As in cpir/cpdr/ldir/lddr, when the repeat condition is met, the CPU generates an extra M-cycle of 5 T-states to decrement PC. This M-cycle performs additional flag changes (discovered and cracked by David Banks (AKA hoglet)), but until now it was not known that MEMPTR is also modified, being set, as in all other block instructions during this M-cycle, to PCi + 1 (PCi = value of PC at the start of the instruction, before it is incremented).
After adding this behavior to my Z80 core, z80memptr.tap from Patrik Rak's Zilog Z80 Test Suite v1.2 fails in the following 2 steps:
Code: Select all
102 INIR->NOP' FAILED
CRC:F3B1BE2F Expected:0A537B63
103 INDR->NOP' FAILED
CRC:F3B1BE2F Expected:0A537B63
Of course, this "new" behavior has been tested on Visual Z80 Remix.
I've opened a pull request to fix Patrik's test suite: https://github.com/raxoft/z80test/pull/3