New open lower RAM module design (photoessay)

[1024MAK]

Here I am only talking about the ‘lower’ or ‘screen’ RAM formed by the 4116 DRAM chips or equivalent DRAM chips, or by a module using SRAM to replace the DRAM.


The ULA is ALWAYS the master. It controls the /RAS and the /CAS.

The Z80 accesses this memory as normal, but the ULA handles the control lines for the Z80A.

The ULA can only read from this memory. There is no requirement for it to write to this memory, hence no write function for the ULA was included in the ULA design.

The Z80A can of course read and write. The Z80 always does a conventional memory access. That is, the first seven address bits are set up, /RAS then goes low. When /RAS goes low, the DRAM should sample the address lines and then latch the address into its internal register.

There is then a short delay. Then the control (“switch”) signal to the multiplexer chips (IC3 & 4) changes state. The multiplexer chips now switch the other seven address bits through to the DRAM address bus.

There is then a short delay for the DRAM address bus lines to settle to their new value.

Now the /CAS line is taken low. When this happens, DRAM should sample the address lines and then latch the address into its internal register. It now has the full 14 bit wide address that it needs. There will be a slight pause while it activates the required memory cell.

If this is a write, it will sample the data line when the /W (write) line goes inactive (high) or when either /RAS or /CAS go high, then store the value in its memory cell.

If it’s a read, it will output the stored value on its output pin and maintain this until when either /RAS or /CAS go high.

You will notice that on the schematic circuit diagram for the ZX Spectrum, each DRAM chip has its data input line (D) directly connected to its data output line (Q).

For ULA reads, it’s slightly different. The ULA uses “page” mode.

The first seven address bits are set up, /RAS then goes low. When /RAS goes low, the DRAM should sample the address lines and then latch the address into its internal register.

There is then a short delay. Then inside the ULA, it switches its outputs so that the other seven address bits go to the DRAM address bus.

There is then a short delay for the DRAM address bus lines to settle to their new value.

Now the /CAS line is taken low. When this happens, DRAM should sample the address lines and then latch the address into its internal register. It now has the full 14 bit wide address that it needs. There will be a slight pause while it activates the required memory cell.

It will output the stored value on its output pin and maintain this.

The ULA will maintain /RAS low, but now changes /CAS to high. I don’t know when the ULA samples the data. But at some point it does.

Next, another seven bit address is output by the ULA. Followed by a slight pause for the address lines to settle. Now the ULA takes /CAS low again.

When this happens, DRAM should sample the address lines and then latch the address into its internal register. It uses the still latched value from earlier for the row address. It now has the full 14 bit wide address that it needs. There will be a slight pause while it activates the required memory cell.

It will output the stored value on its output pin and maintain this. I don’t know when the ULA samples the data. But at some point it does.

When either /RAS or /CAS go high, the DRAM will switch its output off.

The replacement module has to respond in the same manner.

Please note, the above is from my memory, I may post some corrections later if I discover I made any errors.

Mark

[mark8bit]

i have posted some youtube videos (hopefully) to show the sparkles moving this was on the issue 2 with no delay at all, on the game loader screen there are was only one block of them when using delay

[mark8bit]

Interesting theory - do you thing inverter and register would need more than 20ns to do their stuff? RAS to CAS delay time is 20 ns.

i'm thinking it is tiny amounts maybe less than 10ns and possibly enough to cause problems, i would defiantly say that the issue is read only and only ULA read when it is using page mod as such my next plan is try a tiny delay

[dfzx]

Can you tell if those sparkles are read or write problem? If they were read problem I'd expect sparkles move, while if they were write problem, I'd expect sparkles being fixed.

There are never write related problems. The ULA doesn't write to RAM.

The Z80 does all the writes, and the Z80 is much more forgiving with regards to timing. I've never seen any problems related to writes.

[dfzx]

I don’t know when the ULA samples the data. But at some point it does.

That, fundamentally, is the problem. We don't (and can't) know when the ULA samples the data from the bus, which means we need to ensure the data is there for enough time, and that introduces guesswork. Without the ability to tell the exact point in time the ULA collects the data, all oscilloscope traces and calculations based on data sheets go from precise information to just a bit hand-wavy.

It's interesting that the sparkles "dance" - see Mark's videos, which mirror exactly what I saw. To me this implies variation in the video image generation timing. If everything was precise, the sparkles would be static. Which means - maybe? - that the point in time that the ULA collects the data is erratic.

[Pygmalion]

1024MAK

ULA displays the picture, right? Does ULA read RAM all the time while displaying the picture?

If so, if there is problem with ULA reading, picture would NEVER be stable.

[1024MAK]

Yes, the ULA creates the video picture. It reads the 'lower' RAM in real time to feed the shift register (that is clocked by the pixel clock) to generate the video (which before being converted to an analogue signal is a digital bit stream). Except when drawing the borders or during "flyback" when the TV/display is not showing any incoming video signal.

Keep in mind that the will be timing variations for the Z80A. The ULA reads for screen data take priority over the Z80A. If the Z80 attempts to read or write to the 'lower' RAM, or perform an I/O access to the ULA, the ULA will stop the clock to the Z80A, which in turn will "pause" it's operation. The ULA will read the screen data. Then restart the clock to the Z80A, which will then do its read or write. It's important to know that the ULA stops the Z80A before the Z80A gets the chance to access the RAM.

If for any reason, the ULA does not receive the correct data (not that it knows what is correct), it will sample whatever happens to be on it's data pins and transfer it to the internal video circuity. If it's pixel data, you get an 8 pixel random "sparkly" on screen.

If the timing is marginal, it may be an intermittent symptom.

Mark

[mark8bit]

i am tempted to dig another issue 2 out and remove the lower ram so i have another to compare to .. maybe later ..

[Pygmalion]

Yes, data are provided directly from/to Z80, but command lines go through ULA, and it is unclear how ULA converts MREQ RD and WR from Z80 to RAS CAS in WE for DRAM. Additional problem is that ULA processing those lines also makes some additional delay.

What I am concerned is that those sparks can be either from "bad" reading waveforms from ULA or bad data stored in DRAM, and bad data stored in DRAM is because of "bad" writing waveforms from Z80. We cannot conclusively exclude any possibility, so I don't think we can just plainly assume that reading is the problem.

I see data from Z80 are available two clock cycles. Is that 2* (1/3.5MHz) = 570ns for Z80 in Spectrum?

[Pygmalion]

i have posted some youtube videos (hopefully) to show the sparkles moving this was on the issue 2 with no delay at all, on the game loader screen there are was only one block of them when using delay

Interesting videos. It is especially interesting that the sparkles appear only on the part of the screen.

Do I understand right that you get sparkles ONLY when you use ZX Spectrum extensions?

Have you ever seen problems with ZX Spectrum only?

[Pygmalion]

The Z80 accesses this memory as normal, but the ULA handles the control lines for the Z80A.

This detail might be extremely important. How does ULA handle Z80 control lines?

Now the /CAS line is taken low. When this happens, DRAM should sample the address lines and then latch the address into its internal register. It now has the full 14 bit wide address that it needs. There will be a slight pause while it activates the required memory cell.

If this is a write, it will sample the data line when the /W (write) line goes inactive (high) or when either /RAS or /CAS go high, then store the value in its memory cell.

According to the DRAM waveform, data are supposed to be available on lowering /CAS. So I would be surprised if DRAM waited until /W raises. I think it should sample the data as soon as it activates the required memory cell.

And here is the largest difference with the SRAM waveform. SRAM needs some time to get into "read" mode (data lines into float), so data for sampling are supposed to be available only after certain time.

When this happens, DRAM should sample the address lines and then latch the address into its internal register. It uses the still latched value from earlier for the row address. It now has the full 14 bit wide address that it needs. There will be a slight pause while it activates the required memory cell.

It will output the stored value on its output pin and maintain this. I don’t know when the ULA samples the data. But at some point it does.

This is the key question. If ULA samples the data before it changes /CAS back to high there should be absolutely no problem with reading, as both DRAM and SRAM keep data available until this happens. This is how I would bigbang similar communications with various ICs.

I understand 80% of communications but is is the 20% I don't understand/know that are the crucial ones. Such as, when do ULA/Z80 sample data (in relation to control lines)?

[dfzx]

According to the DRAM waveform, data are supposed to be available on lowering /CAS.

No, that wouldn't make any sense. /CAS goes low when the second part of the address (the column address) is on the 7-bit address bus. The memory then has a certain amount of time to fetch the data byte and put it on the data bus.

The 4116 timing diagram is this:



The data is supposed to be on the data bus within t(CAC) time after /CAS goes low. t(CAC) is a maximum of 100ns.

[Pygmalion]

No, that wouldn't make any sense. /CAS goes low when the second part of the address (the column address) is on the 7-bit address bus. The memory then has a certain amount of time to fetch the data byte and put it on the data bus.

The 4116 timing diagram is this:



The data is supposed to be on the data bus within t(CAC) time after /CAS goes low. t(CAC) is a maximum of 100ns.

I was talking about WRITE waveform.

But thanks for sharing the diagram. You see there is tOFF, which is time that DRAM may leave datum available. Minimum is 0ns and maximum is about 20ns. So it makes little sense for ULA to sample datum after raising /CAS low instead of before. SRAM waveform works just the same!

So if ULA samples before raising /CAS, there is no danger of bad reading with either DRAM or SRAM.

[zx64]

Maybe mark8bit is using different memory on his 2 layer board? And it has different timings?

[Pygmalion]

So this thread seems to be at a dead end. I have finished repairing my ZX Spectrum and now have to decide whether to abandon this project and put it back in storage.

I am sure it should be possible to develop the memory module with just a two-layer board. After all, the ZX Spectrum itself is built on a two-layer PCB and the signal lines from the ULA/Z80 to the DRAMs are quite long without this being a major problem.

mark8bit, before I possibly bury this topic, I have two more questions for you:

1. Do the problems with the memory module persist even if no other module is used? I strongly suspect that the external ZX Spectrum test module is a major part of the problem.

2. If you have an extra PCB of the memory module, could you send me one in the post, with me covering the shipping costs and the proportional cost of making the PCB? I have all three chips available, I could do some testing myself.

[winston]

In the interests of thread necromancy, my thoughts on bypass capacitors:

Trying to eliminate them is a false economy. I've just finished a project at work, and when ordering the parts the 0.1uF capacitors were under a penny each even in small quantities. A 0603 size chip capacitor takes seconds to hand solder to the board too. Quite often PCB assembly houses don't even charge you for passive components!

Many of my projects have several per chip (each power pin, e.g. for a CPLD, FPGA or some more complex chip with multiple power pins). For some chips the manufacturer recommends two, a 100nF and 1nF in parallel for each power pin.

You can get some economy from going from 4 layers to 2 but these days I personally don't bother, life's too short to route a moderately complex board on just 2 layers. It makes routing so much easier if youi've got 4 layers and electrical performance much better. It also helps with decoupling - a 4 layer 60mm x 40mm board I just got made at PCBWay, I put it on my LCR meter while unpopulated and was getting around 700pF of capacitance just off the ground and power plane of this small board (on the inner layer the two planes are quite close together).

[Pygmalion]

Trying to eliminate them is a false economy. I've just finished a project at work, and when ordering the parts the 0.1uF capacitors were under a penny each even in small quantities. A 0603 size chip capacitor takes seconds to hand solder to the board too. Quite often PCB assembly houses don't even charge you for passive components!

Many of my projects have several per chip (each power pin, e.g. for a CPLD, FPGA or some more complex chip with multiple power pins). For some chips the manufacturer recommends two, a 100nF and 1nF in parallel for each power pin.

You can get some economy from going from 4 layers to 2 but these days I personally don't bother, life's too short to route a moderately complex board on just 2 layers. It makes routing so much easier if youi've got 4 layers and electrical performance much better. It also helps with decoupling - a 4 layer 60mm x 40mm board I just got made at PCBWay, I put it on my LCR meter while unpopulated and was getting around 700pF of capacitance just off the ground and power plane of this small board (on the inner layer the two planes are quite close together).

I will not argue about the capacitor part. It really is a minor annoyance and not worth the attention.

However, I think it should be possible to develop the module on a two-layer PCB, and the price difference here is significant. After all, the ZX Spectrum itself also works on a two-layer PCB and the traces between ULA and RAM modules are already very long on this board.

I think we are chasing the wrong problem here - if we really knew what the problem was, the solution should probably be very simple.

I have enough experience with bitbanging on various serial and parallel communications to figure out if there is a timing problem knowing the properties of ULA. I am willing to spend my time on this part of the problem, but I can not find the relevant information.

Of course, I can put my ZX Spectrum back in storage and forget all about it. Too bad I already bought the chips for the module.

[dfzx]

However, I think it should be possible to develop the module on a two-layer PCB, and the price difference here is significant.

Earlier in the thread you said the price difference at JLCPCB between an order for 2 layer boards and 4 layer boards is about $5. Here in the UK that's less than the cost of a McDonalds "Big Mac" hamburger. I fully appreciate that what is a small amount of money for some people isn't a small amount for others, but honestly, you're asking people to do a very significant amount of investigation and redesign work on this circuit in order to save pittance.

It's an open source project, you have everything you need to do the work yourself. It sounds like you have the relevant experience, so you should be able to get a 2 layer board made up and do the modifications you want.

[1024MAK]

Okay, best if we calm down.

Right, so there are some points I want to comment on. First off, we now know far more about how high speed digital signals are affected on PCBs now, compared to the 1980s. And Sinclair did have problems. Yes, the ZX Spectrum was okay, but the QL board had to be redesigned. Sinclair discovered various problems during production, and some of these led to parts of the PCB track layout being redesigned. With modifications being required to QLs that had earlier board designs.

With a complex system like a microcomputer system, there are multiple signals changing state regularly. All sixteen address lines may change state at the same time. All eight data lines may change state at the same time. The processor may access the ROM or the 'upper'/'expansion' RAM at the same time that the ULA is reading screen data.

Also, its not simply the "speed" as in frequency of the digital signal. But how fast the fall and rise times of the digital signal are. Modern CMOS chips, such as the SRAM chips, have outputs that have much faster, as in sharper fall and rise times. Plus, the control inputs are also quicker to respond. This later point is important, because it may mean that a spike or other noise on a control line may cause the SRAM chip to respond. Thus completely messing up the intended operation. The 1980s era chips on a ZX Spectrum are a lot slower in comparison. And they are less affected by very short duration unwanted spikes on their control lines (they are unable to respond to such a signal, hence can be said to ignore it).

The effects described in the two paragraphs above may affect signal lines on a two layer board. They may affect a four layer board as well, but because of the ground plane, any effect is likely to be less.

So, it is not just getting the logic right. Or getting the logic levels right. Or getting the timing right. But also getting the noise level to a low enough level that it does not cause problems.

Without having a board in front of me. And without spending many hours with test equipment to carry out various tests.

Mark

[1024MAK]

And the last part of that post appears to have got lost. It should have ended:

'It will be hard to work out exactly what the problem is".

Mark

[Pygmalion]

As for the pure communication protocol, ULA and S80 are masters and RAM is a slave, so the problem with timings is unlikely. Unless ULA is doing something unusual. Unfortunately, knowledge of the ULA communication protocol seems to have been lost to history.

So the hypothesis that the problem is due to noise that could be interpreted as a signal seems the most reasonable. [Maybe that capacitor-resistor combination in the module works as some kind of noise filter...] But if this is the case, I cannot be of any help.

But I am sure someone will eventually figure out what the problem is and how to solve it. Just ping me when that happens. Thanks.

[zx64]

As for the pure communication protocol, ULA and S80 are masters and RAM is a slave, so the problem with timings is unlikely. Unless ULA is doing something unusual. Unfortunately, knowledge of the ULA communication protocol seems to have been lost to history.

Actually, ULA was completely reverse engineered and we know exactly how it works

[winston]

Not only do we know how the ULA works (right down to the transistor level), there's a very good book which will tell you everything you need to know about the ULA:

http://www.zxdesign.info/book/

[winston]

Earlier in the thread you said the price difference at JLCPCB between an order for 2 layer boards and 4 layer boards is about $5. Here in the UK that's less than the cost of a McDonalds "Big Mac" hamburger. I fully appreciate that what is a small amount of money for some people isn't a small amount for others, but honestly, you're asking people to do a very significant amount of investigation and redesign work on this circuit in order to save pittance.

It's even less than that if you're going to make a bunch of them for sale: looking at PCBWay, a suitable 4 layer board, qty 100 will cost
US$123 including shipping, for 2 layer board x 100 of the same size it's $73 including shipping. Going to two layers saves a whopping 50 cents a board (about 39 pence).